Steven Parker
My research focuses on the process technologies that enable modern semiconductor manufacturing, particularly etch, deposition, cleaning, and other critical front-end processes. I study how increasing device complexity changes manufacturing requirements and how equipment suppliers respond to new process challenges. I publish on this website because equipment technology is often hidden behind the final semiconductor product. A processor, memory chip, or advanced accelerator may look like a single component, but producing it requires hundreds of carefully controlled manufacturing steps. Etch, deposition, cleaning, and process control are fundamental to maintaining performance and yield as geometries become more challenging. My work examines equipment intensity across advanced logic, foundry, DRAM, and NAND manufacturing. I follow changes in process flows, layer counts, materials, aspect ratios, transistor structures, and manufacturing techniques that can influence equipment requirements. I also study the connection between equipment innovation and yield. New process technologies are valuable only when manufacturers can achieve acceptable production yields and throughput. This makes process control, equipment productivity, chamber performance, and repeatability important areas of my research. Beyond individual equipment categories, I track semiconductor manufacturers' technology roadmaps and capital spending plans. My goal is to help readers understand why certain equipment markets expand during technology transitions and how process complexity can create new opportunities for equipment suppliers.
Process equipment researcher covering etch, deposition, cleaning, process complexity, yield improvement, advanced nodes, DRAM, NAND, and foundry manufacturing.
Steven Parker is a semiconductor process equipment researcher focused on the manufacturing technologies used to build increasingly complex semiconductor devices. His primary areas of coverage include etch, deposition, cleaning, process control, and related front-end equipment.
Steven examines how changes in transistor structures, device architectures, materials, layer counts, and process flows influence equipment intensity. His research spans advanced logic, foundry, DRAM, and NAND manufacturing.
Yield and process control are central themes in his work. As manufacturing becomes more demanding, equipment repeatability, chamber performance, process uniformity, and productivity become increasingly important to successful volume production.
He also studies the relationship between equipment innovation and semiconductor technology roadmaps. New manufacturing approaches can require additional process steps or different equipment capabilities, creating changes in the competitive landscape for equipment suppliers.
Through his articles, Steven provides readers with a technology-focused view of semiconductor equipment and explains how process complexity, manufacturing yield, and advanced-node development translate into equipment demand.
His Articles
NAND vs. DRAM ETF Divergence: The Trading Strategy
Memory markets don't move in lockstep. NAND flash and DRAM—though both essential to AI infrastructure—operate on different supply-demand cycles, face distinct technological constraints, and respond to different end-market drivers. Yet most semiconductor ETFs treat memory as a monolithic bet, lumping NAND and DRAM producers together and forcing investors to take undifferentiated exposure.
Samsung’s 471% Memory Revenue Surge: Decomposing the AI-Driven Earnings Explosion
A 471% increase in memory revenue is not a routine cyclical rebound. It is a signal that pricing, product mix, and customer demand have moved together with unusual force. For Samsung, the headline captures something larger than a strong quarter: artificial intelligence is changing where the semiconductor industry earns its money—and who ultimately pays for that transformation.
Interpreting the Sentiment Signal as Wafer Fab Utilization Breaches 85%
Wafer fab utilization is one of the semiconductor industry's most closely watched operational metrics. When utilization climbs above key thresholds, it has ripple effects across pricing, lead times, equipment demand, supplier margins, and market sentiment.
Thermal Simulation Challenges and Solutions in 3DIC AI Chip Design
As AI workloads push chips to deliver ever higher compute density, designers are increasingly turning to three‑dimensional integration (3DIC) to stack dies vertically and pack more functionality into limited footprints. While 3DIC architectures unlock significant performance and bandwidth advantages, they also introduce complex thermal behaviors that are far harder to predict and manage than in traditional 2D layouts.
Inventory Adjustment Done – Lead Times Shorten to Normal Levels
The semiconductor industry has finally exited a long and painful inventory adjustment phase. After years of oscillating between shortages and surplus, channel inventories and supplier stock levels have normalized, and lead times for many critical components are returning to what manufacturers recognize as “normal” ranges.
Edge AI NPU Penetration in AI PCs and Smartphones Exceeds 40%
As edge artificial intelligence has shifted from novelty to necessity, one metric captures the depth of that change: neural processing unit (NPU) penetration in client devices. When more than 40% of newly shipped AI PCs and smartphones include dedicated NPUs, it signals a structural transition in how compute is architected at the edge.
Tactical Asset Allocation Recommendations for Semi ETFs in 2H 2026
Semiconductor themed ETFs walk into the second half of 2026 in a very different environment than a year ago. AI infrastructure spending is still strong, but leadership has narrowed and valuations in some names have stretched. Memory and HBM cycles are gaining momentum, equipment orders are running through another capex wave, and regional policy stories continue to shape A‑share and Korea exposure. That mix makes semis both attractive and tricky. Tactical allocation is about leaning into the parts of the theme that still have room while respecting the growing risk of disappointment and rotation.