Nathan Collins
I focus on the semiconductor technologies behind AI training and inference systems. My research covers compute density, accelerator performance, advanced process nodes, chiplet architectures, high-speed interconnects, memory systems, and data-center deployment. I am especially interested in the relationship between system requirements and the physical limitations of semiconductor manufacturing. I write for this website because AI computing performance cannot be explained by processor specifications alone. The final performance of an AI system depends on the interaction between compute units, memory bandwidth, communication links, packaging, software, power delivery, and cooling. My goal is to explain these relationships in a clear and technically grounded way. My work examines the evolution of AI accelerator architectures and the growing use of chiplets and heterogeneous integration. As semiconductor designs become more complex, system designers increasingly divide functions across multiple dies and combine different process technologies within one package. I follow how these approaches affect performance, cost, yield, and manufacturing requirements. I also research the infrastructure surrounding AI computing. Data-center accelerators require high-speed networking, advanced memory, efficient power systems, and sophisticated thermal solutions. These supporting technologies are important parts of the semiconductor ecosystem and can influence the pace of AI infrastructure deployment. In addition to technical research, I monitor the industry and investment implications of AI semiconductor development. I aim to connect architecture and manufacturing trends with foundry demand, packaging capacity, memory requirements, and the broader semiconductor supply chain. My articles are intended to help readers understand the complete system behind AI computing growth.
AI compute technology researcher focused on accelerator performance, chiplets, advanced nodes, interconnects, memory systems, and data-center infrastructure.
Nathan Collins is an AI compute technology researcher who studies the semiconductor architecture and infrastructure behind AI training and inference systems. His work on this website connects processor design with manufacturing and system-level requirements.
Nathan examines compute density, accelerator performance, advanced process nodes, chiplet architectures, high-speed interconnects, memory systems, power delivery, and cooling. His research explains why the performance of an AI system depends on the interaction of many semiconductor and infrastructure components.
A central part of Nathan's coverage is the development of chiplet-based and heterogeneous architectures. As advanced processors become more complex, designers are using multiple dies and process technologies to improve performance, flexibility, and manufacturing efficiency. Nathan explores the technical and economic implications of these approaches.
His research also covers the supporting infrastructure required by AI accelerators. Networking, high-bandwidth memory, advanced packaging, power systems, and thermal solutions all influence the deployment of modern AI computing platforms.
Through his articles, Nathan provides readers with a system-level understanding of AI semiconductors and explains how architecture, manufacturing, packaging, and data-center infrastructure combine to shape the future of computing.
His Articles
Chip IPO Wave in 2026: What CXMT’s $33B Listing Bid Means for Global DRAM Pricing
CXMT’s public-market funding strengthens its ability to challenge established DRAM suppliers, but an IPO does not immediately create cheaper memory. The pricing effect depends on how quickly capital becomes qualified output—and whether that output arrives before demand weakens.
The Post-Moore Path for AI Chips: Advanced Packaging Succeeds Process Scaling
For decades, the semiconductor industry rode a remarkably simple storyline: shrink transistors, pack more of them onto a die, and enjoy automatic gains in performance and efficiency. That story—embodied in Moore’s Law—still matters, but for AI chips in the mid‑2020s it is no longer the sole, or even primary, driver of progress.
A Full Mapping of HBM-Themed Targets in the A-Share Market
As High-Bandwidth Memory (HBM) becomes a core enabler for AI, high-performance computing and advanced graphics, China’s domestic capital markets have seen a rapid expansion of “HBM concept” stocks and supply-chain plays. While the most advanced HBM die and module production remains concentrated in Korea and the United States, a growing number of A-share listed companies participate in the broader HBM ecosystem—through equipment, materials, packaging, substrates, thermal solutions, and peripheral components.
Commercialization Progress of Neuromorphic Chips: 2026 Application Scenario Validation
Neuromorphic chips have occupied a fascinating space in the semiconductor and AI worlds for more than a decade: rich in promise, modest in revenue, and frequently described as “five years away” from mainstream adoption. By 2026, however, the conversation has shifted. While neuromorphic hardware is still far from displacing GPUs or general‑purpose accelerators, we now see concrete application scenarios where these chips are moving out of labs and pilot projects and into commercial trials, edge products, and specialized services.
China’s HBM Localization Progress: The Catch-Up Pace of CXMT and XMC
China’s drive to localize advanced memory technologies has accelerated over the past several years. High-Bandwidth Memory (HBM) sits near the center of that strategy because it is integral to AI accelerators, high-performance computing (HPC) and other strategic compute platforms. Two domestic players—ChangXin Memory Technologies (CXMT) and XMC (Xianghui Memory, commonly referred to as XMC)—have become focal points in assessing how quickly China can close the gap with international incumbents on HBM die, stacking, and packaging.